Protection of CMOS output drivers

Every computer chip needs on-chip ESD protection at its interfaces. Integrated circuits have different kinds of interfaces. This article discusses approaches to protect output drivers. This article compares different options for output drivers, focused on the NMOS transistor because that is the most sensitive part and is easily damaged during ESD stress.

Applying System level ESD (IEC 61000-4-2) stress on ICs

Despite the fact that IEC 61000-4-2 is a standard created for system level ESD stress it is frequently used for stand alone integrated circuits. The test approach for chips is not defined nor standardized for this requirement so it is important to have a discussion on the test conditions and acceptance criteria. This article outlines 3 aspects that need to be considered if on-chip ESD protection needs to withstand the IEC 61000-4-2 stress

ESD protection for 2.5D and 3D packages

More and more companies are turning to advanced semiconductor packaging. This trend has an effect on ESD protection. Earlier in 2021, Sofics submited a paper for the IP-SOC USA conference about ESD protection for 2.5D and 3D packaging. The abstract, the presentation and video are available here.

ESD protection for SOI technology

SOI technology introduces several challenges for the ESD designer. This article provided more background and example data on these issues. Fortunately, there are several ways to overcome those challenges. Sofics has supported IC companies with novel ESD concepts that improve IC performance and increase the ESD robustness.

Comparing 22nm CMOS, 22nm SOI and 16nm FinFET technology (part 2)

IC designers that develop a new integrated circuit have many different foundry and process options. There are several aspects that need to be considered to make a rational decision and select the optimal process. One of those items is on-chip Electrostatic Discharge (ESD) protection. This article compares the properties of the major ESD device types for 3 process options: CMOS (22nm), thin-film FD-SOI (22nm) and first generation FinFET (16nm) technology.

Comparing 22nm CMOS, 22nm SOI and 16nm FinFET technology (part 1)

IC designers that develop a new integrated circuit have many different foundry and process options. There are several aspects that need to be considered to make a rational decision and select the optimal process. One of those items is on-chip Electrostatic Discharge (ESD) protection. This article compares the properties of the major ESD device types for 3 process options: CMOS (22nm), thin-film FD-SOI (22nm) and first generation FinFET (16nm) technology.

CDM robustness of SCR protection devices

We often get the question: what is the CDM robustness of your ESD protection circuit? Though the question is clear, it is very hard to formulate a meaningful answer. CDM qualifies the performance of an IC or die in a specific package. Nevertheless, one expects an answer for the ESD circuit expressed in Volts.

This article discusses how VF-TLP analysis can be used to assess the CDM current capability of ESD devices.

ESD protection of interfaces with thin gate oxide transistors

How do you protect chip interfaces that require thin gate (core) transistors in advanced CMOS, SOI of FinFET processes? How do you ensure sufficient ESD robustness? Conventional ESD protection is not sufficient. Discover the background for that and a solution as well in this article. The answer is found in a strategy of local clamping with power-efficient devices.

Adapting Diode triggered SCRs (part 2)

In this article, I wish to introduce you to how we can use diode triggered silicon controlled rectifiers (DTSCRs) for on-chip ESD protection. I will explain how its 3 main parameters – trigger voltage, holding voltage and failure current – can be tuned in order to protect ICs with very different characteristics.