Selecting optimized ESD protection for CMOS image sensors

The market for CMOS image sensors (CIS) is projected to grow with a Compound annual growth rate (CAGR) of 7 to almost 9% in the next 5 years. According to researchers it will reach a total yearly value of nearly $30B by 2026 (link 1, link 2, link 3).

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CMOS imagers are used in many different markets. Consumer electronics (e.g. smartphones) represents the biggest part but the sensors are also used in surveillance and security, space, healthcare and automotive products. That last segment is actually growing faster than the total CIS market. The number of image sensors per car is increasing quickly both for viewing as for ADAS type of functionality. The total market value in automotive is projected to double from 2018 to 2024, according to Yole (link).

The technology behind CMOS imagers has seen a lot of evolution. That is needed to enable higher resolutions (number of pixels), faster capture (more frames per second), better image quality under low light settings, higher number of colors that can be recognized, and several other improvements.

The image sensors are always combined with other silicon chips like memory, compute and Artificial Intelligence (AI) devices. Some functions can be integrated on the sensor but recently 3D chip-stacking is used to integrate multiple dies in a single package.

At Sofics we have supported several companies that develop image sensors for consumer, automotive and security applications. The article below provides a summary about the 3 main aspects that IC designers need to consider when selecting the ESD protection clamps for their image sensor projects.

1. High-speed communication lines

IC designers use different interfaces like MIPI, V-by-one, LVDS, SerDes, USB, PCIe, … to connect the image sensor to the next block in the chain. The image data is transferred to screens, memory or AI/compute devices. With a growing number of pixels, increased frame rate and more bits per pixel, the amount of data to be transferred is exploding. To enable this increase in data rate the parasitic capacitance of the ESD protection must be reduced. Conventional ESD clamps introduce parasitic capacitance of more than 200fF.

Sofics engineers have developed ESD protection clamps that have 30% to 50% lower parasitic capacitance compared to conventional concepts for the same ESD robustness. These solutions have been used for interface data rates above 10 Gbps.

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IC designers also need to use thin oxide transistors for the communication interface circuits. However, these transistors are easily damaged under ESD stress. The ESD design window (link) is very narrow. This means that IC designers need to use ESD protection concepts with a low trigger voltage (link).

2. 3D hybrid integration

While 3D die-stacking is still a complex operation for chip assembly makers, it simplifies the sensor design. Each function (memory, ADC, compute, sensor) can be designed in the most appropriate process technology.

  • DRAM and Flash memory chips are typically built using custom processes that include small area capacitors (DRAM) or 3D NAND cells.
  • The sensor chip (CIS) uses a mainstream CMOS like 90nm or 65nm. The CIS foundry provides extra options like color filters and lenses.
  • Compute and AI functions on the other hand are produced on the most advanced CMOS or FinFET processes to reach the highest performance.
From Sony: The evolution and future trend of CMOS image sensor 3D stacking architecture (link)

There are several reasons why it is important to use custom ESD solutions for 3D stacked assemblies.

  • Conventional ESD concepts, provided by most foundries, are suited for an entire I/O ring. However for 3D stacked assemblies, IC designers use small I/O segments scattered around the die, each segment close to the Through Silicon Via (TSV). An approach with local I/O clamps provides much more flexibility (link).
  • Die-2-die interfaces can operate at a lower voltage (e.g. 1.0V or lower) compared to the typical I/O cells (1.8V, 2.5V) and a reduced drive current. The interfaces can then also be designed using smaller thin oxide devices. An adequate ESD protection approach is required to protect the sensitive circuits (link).
  • Because die-2-die connections are established in ESD-safe environments the ESD robustness level is typically reduced. Compared to conventional IC pins that require 2kV HBM, the assembly service provider can ensure high yield even at 200V HBM.

More information about custom ESD solutions for 2.5D and 3D applications can be found here (link).

3. High and low voltage interfaces

Many sensor chips are built using 90nm, 65nm or more advanced CMOS technology. In those process nodes, foundries offer I/Os for 1.8V, 2.5V and sometimes 3.3V. However, several interface types still require 5V tolerance. For example, I²C interfaces are open-drain I/Os that connect to an external 5V bus. Also for USB interfaces 5V operation is sometimes required. If the camera module is battery powered it needs to tolerate more than 4.5V.

But imagers also require support for negative voltages at the I/Os. A -1V negative bias circuit requires a different ESD approach. The typical diode between Vss and I/O practically prevents bias voltage below -0.3V.

Sofics has delivered custom, local ESD clamps both for a higher and lower/negative interface voltage range.

Conclusion

IC designers working on novel CMOS image sensor products require dedicated attention for ESD protection to enable faster data rates, to reduce I/O circuit area and tolerate a broader voltage range.

Sofics has supported several CMOS sensor projects for customers in Asia, Europe and USA. Our engineers also delivered custom ESD clamps for circuits that link with CMOS imagers. Feel free to connect to discuss your IC design.

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Published by Bart Keppens

Chief Business Development at www.sofics.com Sofics is a foundry independent semiconductor IP provider that has supported 100+ companies worldwide with customized/specialty Analog IOs and on-chip ESD protection. Fabless companies using Sofics IP can enable higher performance, higher robustness and reduce design time and cost. Our technology has been characterized on 11 foundries including advanced nodes at TSMC, UMC, GF, Samsung Foundry.

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