Latch-up in CMOS circuits: threat or opportunity (part 2)


Latch-up refers to unwanted short circuits which can occur in an integrated circuit whereby the power supply is inadvertently connected to the ground. In the first part (threat) [Link] of the article the focus was on the threat of latch-up and different ways to prevent it. In this part (opportunity) we discuss how (parasitic) SCR devices can be used in a positive way.

Basic SCR schematic (left), Cross section (middle), IV characteristic (right)

SCRs used for ESD Protection

Typically, in CMOS IC design, we always think about avoiding latch-up. At the same time, another issue which is of concern for CMOS IC designers is that of protection against ESD and other transient events. The inherent tendency of the parasitic SCRs to latch-up and deteriorate chip performance can be exploited to protect it against ESD damage. We should control how/when latch-up occurs and create a safe path through which a large current generated by ESD or other unwanted transient events can be safely routed to the ground.

In more concrete terms, we need to engineer a system whereby when an ESD or other unwanted transient event occurs, the SCR triggers and safely guides the current to the ground. On the other hand, when the chip is operating normally, we need the SCR to be turned off and have no effect on the circuit. From our understanding of an SCR’s operating mechanism, this means we need to effectively control (depending on the application);

  1. The holding voltage (Vh) – below the holding voltage, the SCR does not conduct current. Our ESD protection scheme is part of the circuit but it should not affect circuit performance. Any I/O voltage within the appropriate domain i.e. below the circuit’s power supply voltage (Vdd) should not trigger the SCR. Accordingly, the SCR should be engineered such that it’s holding voltage is greater than Vdd i.e. Vh > Vdd.
  2. The trigger voltage (Vt1) – a signal beyond a certain threshold would trigger an SCR. We can make sure the SCR is engineered such that it is triggered into the latched state if the I/O voltage exceeds a certain precise threshold. However, depending on the device geometry and intended application, there is an upper bound on Vt1 since we need to prevent ESD from damaging the chip. This upper bound is the oxide break down voltage for an input or the drain-source breakdown voltage for an output interface. On the other hand, we also need to make sure Vt1 > Vh as we don’t want I/O voltages lower than Vdd to trigger the SCR.
  3. The on resistance (Ron) – Ron should be low enough to ensure the voltage drop (Vh + Ron*Iesd) over the SCR is lower than the failure voltage of the functional circuit.
  4. The failure current (Imax) needs to be high enough to allow for adequate discharge of the transient charges to the ground.

An SCR fulfilling the requirements described above is an excellent active ESD protection element for typical CMOS ICs. Given the possibilities explored here, it is evident this SCR-based ESD protection scheme is highly customizable. It can be adapted to the specific application targeted by the IC. These type of devices become even more relevant nowadays given the wide range of applications like IoT, telecom, medical, automotive etc. Each of these applications need to fulfill unique requirements. Consequently, SCR-based ESD protection circuits can be a great tool in the arsenal of an IC designer.

In the first part, we addressed the issue of latch-up as it is commonly encountered in CMOS IC design. We analyzed its origin and sought to explain how it can have a negative effect on IC performance. We then proceeded to discuss ways in which it can be prevented. In this second part, we considered latch-up issues as an opportunity rather than a threat to IC performance. Finally, we discuss how our understanding of latch-up can be used to develop ESD protection circuits for ICs used in various applications. In our discussion, we highlight the design rules which should be followed to realize an SCR based ESD protection circuit in ICs.

More information?

In an article about Diode Triggered SCRs [Link] we provide a clear explanation how the device behavior can be adapted to ensure it can be used as an ESD protection solution while preventing latch-up issues. In a cooperation with the ESD experts at Oki (now Lapis semiconductor) we presented a summary about the use of SCR devices for ESD protection. [Link].

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