Latch-up in CMOS circuits: threat or opportunity (part 1)


Latch-up refers to unwanted short circuits which can occur in an integrated circuit whereby the power supply is inadvertently connected to the ground. Complementary Metal Oxide Semiconductor (CMOS) is the dominant technology for manufacturing today’s integrated circuits (ICs). Among other things, CMOS technology owes its dominance to two key features. Namely, high noise immunity and low power consumption. Despite these advantages, the typical CMOS device geometry (as shown in the picture below) is particularly well suited to the formation of parasitic bipolar junction transistor (BJT) devices.

Simplified cross section of a CMOS inverter stage with NMOS (left) and PMOS (right) tranistors. The parasitic PNP and NPN bipolar transistors could cause latch-up when a poisitive feedback is formed.

Latch-up Mechanism

The parasitic BJTs in the CMOS inverter structure form a positive feedback loop. This is inevitable since the collector of one BJT is connected to the base of the other (and vice versa). It is well known that the large collector current of a BJT is driven by a much smaller base current. Now, if for some reason (e.g. a small external disturbance) a collector current flows in one of the BJTs, it will be fed into the base of the other BJT. 

This generates an even greater collector current in the latter BJT which is then fed into the former BJT. When the BJTs become locked in this runaway positive feedback process, they are said to be latched. In this latch-up condition, a low-impedance path is created between the chip’s power supply and ground. A large current flows through the CMOS chip. As a result, the chip may not function as designed and could eventually become damaged. 

The parasitic BJTs described above form a device which is equivalent to a thyristor or silicon controlled rectifier (SCR). An SCR is a PNPN device that is used a lot in high power electronics as a dynamical control circuit element. In that case, the 3 terminals of an SCR are typically labelled as gate, anode and cathode. In an SCR, current flow from the anode to the cathode (i.e. latch-up) is triggered by a small signal applied to the gate terminal. This current continues to flow even after the trigger signal has been turned off. The SCR can only be turned off if: 

  1. The current flowing through it drops below a critical threshold. This is the so-called holding current.
  2. The power in the whole circuit is turned off (below the holding voltage) or reset.

Latch-up Causes

In the case of a CMOS chip, various signals can act as a trigger to latch a parasitic SCR. We have three main possibilities here:

  1. The first possibility is the situation where the voltage applied to the chip’s pins is a lot higher than its power supply voltage, causing a breakdown of the Nwell/Pwell.
  2. Secondly, an electrostatic discharge (ESD) event can trigger the parasitic SCR given the large currents/voltage which typically accompany it.
  3. Finally, ionizing radiation (e.g. in space or nuclear environments) can also trigger latch-up in the parasitic SCR.

Latch-up Prevention

In view of its negative effects on device performance, latch-up prevention is a key concern for CMOS IC designers. There are a variety of methods commonly employed to prevent latch-up. These prevention schemes are closely linked to the typical sources of latch-up mentioned earlier.

  • The first option is to ensure that the voltages sent into the chip remain below the maximum voltage ratings of the chip. Unfortunately, this method is rather ineffective against unpredictable events like ESD or other unwanted transients.
  • The second option entails including oxide trenches and buried oxide layers to isolate NMOS and PMOS devices. This means additional processing steps and a rather complex device structure.
  • Finally, another commonly used method involves increasing the distance between NMOS and PMOS devices and placing guard rings between devices.

More information?

In summary, we started by addressing the issue of latch-up as it is commonly encountered in CMOS IC design. We analyzed its origin and sought to explain how it can have a negative effect on IC performance. We then proceeded to discuss ways in which it can be prevented.

Typically in CMOS IC design, we always think about avoiding latch-up. At the same time, another issue which is of concern for CMOS IC designers is that of protection against ESD and other transient events. The inherent tendency of the parasitic SCRs to latch-up and deteriorate chip performance can be exploited to protect it against ESD damage. In a second part (link) we discuss how Silicon Controlled rectifiers can be used exploited.

Latch-up events in semiconductor devices can create a lot of problems. Fortunately, the typical causes have been studied and documented by several authors. Sofics engineers have also supported several customers. We have also created a tutorial about latch-up causes and prevention. Contact us if you like to discuss your design.


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