At Sofics, we specialize in overvoltage-tolerant I/O’s. However, the term “overvoltage tolerant I/O” can mean different things to different people. For some, it might simply refer to a circuit that can withstand high voltages. Others may interpret it as a voltage higher than what the technology permits. Still, others might equate it to an open-drain circuit.

To engage in a meaningful discussion about the necessary “overvoltage tolerant” requirements, we need to establish clear and unambiguous terminology.

System definitions

First, let’s examine the supplies. We have V_DD, which represents the core voltage, and V_IO for the I/O supply voltage. V_DD is the voltage domain of signals entering and exiting the chip’s core, while V_IO powers the I/O. Additionally, V_SS is the minimum voltage connected to the I/O, typically ground. Some suppliers refer to V_IO as VDDPST.

Next, lets take a look at the technology. Here, the most important parameter is the Vmax of the devices used. This is the maximum allowed voltage between two pins of the device. If we go above this voltage, we have an SOA violation and eat into the lifetime of our device. SOA stands for Safe Operating Area, and indicates which voltage levels are safe to operate a device at. Typically, the Vmax of a device is its voltage rating +10%.

While the maximum voltage is often the same for all pin combinations of a device, exceptions exist. For example, a HV LDMOS can handle up to 100V drain-source voltage but will fail if the gate-source voltage exceeds 5V.

Finally, lets take a look at the voltages on the pad. The actual pad voltage is called V_pad. This can be anywhere between V_SS and V_bus. V_bus is defined as the maximum possible voltage that can be present on the pad. In a basic GPIO, V_bus is identical to V_IO.

Case 1: V_IO > V_max

The clearest case of an overvoltage condition is if the voltage is higher than what the devices in the technology allow.

For instance, consider a 5V I/O in 28nm technology. By default, there are no 5V capable devices in this technology, so a standard design for a 5V I/O is not possible. A custom overvoltage tolerant design is required.

A second example of this case is seen in radiation hard applications. Here, charges get trapped in the thick gate oxides, increasing device leakage substantially over the lifetime of the device. Sometimes so severely that there is no difference seen between the transistor ON and OFF states. This environment calls for a custom design using only thin gate oxides. This is why we have delivered a 1.2V GPIO in 28nm technology making use of only 0.9V thin gate core transistors. (Datasheet)

Lastly, we could avoid certain devices to reduce costs. Omitting certain high voltage devices lessens the number of masks required for production, thereby lowering the cost per IC.

Case 2: V_bus > V_IO

A second major overvoltage case is when the bus voltage can go higher than the VIO: the voltage connected to the I/O. If this happens, the body diode in the PMOS driver starts conducting, leading to huge pad currents.

This is bad news for both our own chip as well as the external factor driving the bus. Our own supply gets extra current through the bus, which could increase the VIO voltage to unsafe levels. The external factor driving the bus is also not happy about this situation: it is probably a driver actively driving the bus high. Since it is not able to do this, it will consume a huge amount of current while not even maintaining communication.

A second issue in this case is that a lot of overvoltage tolerant drivers use intermediate voltages to protect their individual devices. However, if your supply is not high enough to be able to generate these voltages, this is not an option anymore. Generating the intermediate voltages from the higher pad voltage is possible, but comes with significant pad loading and design complexities due to the non-stable pad voltage.

A common solution to this issue is using an open drain architecture. The I2C protocol is an example of this.

Another example: cold spare / supply shutdown

Case 2 overvoltage tolerance examples

Most circuits are designed with a possible voltage variation of ±10%. This does not only have implications on the circuit design, but also on the application design. In this example, we have two identical 5V I/Os that are communicating on the same bus. The only difference between the two is their supply voltage. One is +10% (5.5V) while the other is -10% (4.5V). Since both I/Os are on a different chip, this scenario is possible. If the first I/O now drives the bus high to its supply of 5.5V, the second I/O will see a bus voltage 1V higher (more than a diode drop) than its local supply voltage of 4.5V, leading to a case 2 overvoltage tolerance and all issues that come with it.

A major danger of this issue is that it will often only be seen in the field. If you do not explicitly test this case, either in simulation or in the lab, you will not see it until it is in the field.

Another example of a case 2 overvoltage is a low-power chip or cold spare where the supply is shut down when not in use. This again leads to a VIO = 0V < Vbus. In other words, if you don’t specifically design your I/O for these cases, you will not be able to correctly shut down your supply while being connected to the bus.