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Optimized Low Parasitic Capacitance ESD Clamps for High-Bandwidth 2.5D/3D Chiplet Interfaces in Advanced FinFET Technology
15th anniversary of Sofics – June 26
Breakthrough in area efficiency of on-chip ESD protection.
Protecting die-2-die interfaces…
Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology
Optimized Local I/O ESD Protection in FinFET Technology for 2.5D and 3D hybrid integration
Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology
ESD protection of interfaces with thin gate oxide transistors
ESD protection for 2.5D and 3D packages
Optical communication also requires ESD protection
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