Enable higher performance
Increase ESD robustness
Reduce time and cost
Analog I/Os and ESD protection for
your next TSMC 5nm FinFET design.
Most foundries provide GPIO libraries for free. These libraries contain power/ground cells, analog I/Os, digital I/Os. However, for some applications the general purpose library introduces limitations. Sofics developed solutions to extend the GPIO libraries.
Interface solution with low parasitic capacitance
While general purpose analog I/Os are suitable for most interfaces, high-speed communication (Wired, wireless or optical) needs a special solution. The traditional ESD concepts introduce a lot of parasitic capacitance. Sofics has created ESD protection with low-parasitic capacitance to enable 112Gbps datarates.
Interface solution for low-voltage I/Os below 1.8V.
For TSMC 5nm, the GPIO libraries focus on 1.2V or 1.5V I/O solutions. Sofics developed analog I/Os for 0.75V interfaces in TSMC 5nm FinFET. IC designers connect thin oxide transistors directly to the pad so effective ESD protection is a must.
Low leakage interface solutions
Typical GPIO libraries use traditional ESD concepts like self-protective output drivers and BigFET rail clamps that introduce a lot of standby leakage. Sofics developed improved solutions that can reduce standby leakage by 100x or more.
Any ESD robustness level
Most of the GPIO libraries are designed for 2kV HBM ESD robustness. However IoT, automotive, industrial and consumer applications sometimes need higher robustness. The Sofics proven methodology allows us to customize the on-ESD protection devices for any robustness level.
Higher voltage tolerance like 3.3V
IC designers sometimes need an interface that can tolerate a higher voltage level, beyond the maxmim from the foundry GPIO library. Sofics engineers have proven 3.3V solutions in most CMOS/FinFET processes.
5nm – Library contents
- Low-leakage ESD power clamps for different voltage domains (0.75V – 3.3V).
- Analog I/Os for the different voltage options with full local ESD protection so there is no need to worry about power bus resistance.
- Solutions for high-speed communication with low parasitic capacitance. Cells can be adapted for your requirement. Example: 100fF for 1kV HBM.
- Analog I/Os with higher voltage tolerance or overvoltage tolerant for hot-swap, cold-spare, failsafe interfaces.
Fabless companies using Sofics IP can enable higher performance, higher robustness and reduce design time and cost.
Sofics is a foundry independent semiconductor IP provider that has supported 100+ companies worldwide with customized/specialty Analog I/Os and on-chip ESD protection. The technology has been characterized on most CMOS processes, as well as on SiGe, SOI, BCD and advanced FinFET nodes like 16nm, 12nm, 7nm, 6nm and 5nm.
Request a copy of our measurement report
Contact us to get a copy of our TSMC 7nm measurement report.
Battery powered applications
IC designers have integrated Sofics ESD in systems running for 10-years on 1 coin battery. The leakage of our ESD cells is 100x lower compared to conventional approach. Huge improvements can be made in stand-by, sleep, operational modes and during power-cycles.
One of the key challenges designers struggle with is the need to limit the parasitic capacitance at the interface pads. Sofics engineers have delivered ESD protection with low parasitic capacitance (50fF or lower) for optical, wired and wireless interfaces.
Enable signal voltage below/beyond standard levels
Some applications require Analog I/Os for voltage below or beyond the IO library voltage limits. Sofics has proven ESD solutions to allow 3.3V and 5V applications in most processes.
Using Sofics’ ESD solutions we significantly lower our technical and business risks and expenses.
Kenji Numata, Senior manager, Toshiba semiconductor company