Enable higher performance
Increase ESD robustness
Reduce time and cost
1.2V Analog I/Os for
your next TSMC 65nm IC design.
Most foundries provide I/O libraries for free. However, for some application types the general purpose I/Os (GPIO) introduce several limitations. For TSMC 65nm, the GPIO libraries mostly focus on 1.8V, 2.5V or 3.3V I/O solutions.
Many applications require 1.2V interfaces.
Sofics developed an I/O library for 1.2V interfaces in TSMC 65nm. The cells do not rely on thick oxide transistors to ensure long lifetime even during sustained radiation.
- Low leakage ESD protection cells
- Small area
- 50um pitch
- Over-voltage tolerant option – no diode to Vdd for cold-spare, hot-swap interfaces
- Low capacitance local clamp (<200fF, <130fF options)
- Power clamp for the 1.2V core area and another version for the 1.2V IO area [Data sheet]
- 1.2V Analog I/O with full local ESD protection and integrated power clamp – no need to worry about power bus resistance [Data sheet]
- 1.2V Analog I/O with full local ESD protection and integrated power clamp and integrated CDM secondary protection [Data sheet]
- 1.2V Analog I/O with over-voltage tolerant local ESD protection [Data sheet]
- Power cut cell to separate 1.2V interface area from TSMC GPIO sections
Fabless companies using Sofics IP can enable higher performance, higher robustness and reduce design time and cost.
Sofics is a foundry independent semiconductor IP provider that has supported 100+ companies worldwide with customized/specialty Analog I/Os and on-chip ESD protection. The technology has been characterized on most CMOS processes, as well as on SiGe, SOI, BCD and advanced FinFET nodes like 16nm, 12nm, 7nm, 6nm and 5nm.
Request a copy of our measurement report
Contact us to get a copy of our TSMC 65nm measurement report.
Battery powered applications
IC designers have integrated Sofics ESD in systems running for 10-years on 1 coin battery. The leakage of our ESD cells is 100x lower compared to conventional approach. Huge improvements can be made in stand-by, sleep, operational modes and during power-cycles.
One of the key challenges designers struggle with is the need to limit the parasitic capacitance at the interface pads. Sofics engineers have delivered ESD protection with low parasitic capacitance (50fF or lower) for optical, wired and wireless interfaces.
Enable signal voltage below/beyond standard levels
Some applications require Analog I/Os for voltage below or beyond the IO library voltage limits. Sofics has proven ESD solutions to allow 3.3V and 5V applications in most processes.
Sofics offered us a silicon proven portfolio and fast time to market. Within just a few weeks we went from first contact to contract to solution delivery.
Phil Horsfield, VP Silicon at Graphcore