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Consulting session or tutorial about
on-chip ESD protection
Every Integrated Circuit (IC) needs on-chip ESD protection at its interfaces. Most foundries provide GPIO libraries. These libraries also include ESD protection. However, for some applications the general purpose I/O are not good enough.
Sofics experts have supported 100+ fabless companies
with unique or customized solutions.
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Sofics is a foundry independent semiconductor IP provider that has supported 100+ companies worldwide with customized/specialty Analog I/Os and on-chip ESD protection. The technology has been characterized on most CMOS processes, as well as on SiGe, SOI, BCD and advanced FinFET nodes like 16nm, 12nm, 7nm, 6nm and 5nm.
Battery powered applications
IC designers have integrated Sofics ESD in systems running for 10-years on 1 coin battery. The leakage of our ESD cells is 100x lower compared to conventional approach. Huge improvements can be made in stand-by, sleep, operational modes and during power-cycles.
One of the key challenges designers struggle with is the need to limit the parasitic capacitance at the interface pads. Sofics engineers have delivered ESD protection with low parasitic capacitance (50fF or lower) for optical, wired and wireless interfaces.
Enable signal voltage below/beyond standard levels
Some applications require Analog I/Os for voltage below or beyond the IO library voltage limits. Sofics has proven ESD solutions to allow 3.3V and 5V applications in most processes.
We selected Sofics’ ESD/EOS protection: lower cost than building the clamps from scratch.
Frank Shulze, Sensing and Automotive,
ZMDI, now Renesas Electronics Germany