on-chip ESD protection, custom/specialty I/O and PHY circuits
Fabless semiconductor companies usually use third-party IP blocks when developing ICs. An important IP is on-chip ESD protection. Caution must be exercised in choosing the right ESD IP to avoid patent infringement and inefficient ESD clamps.
Thomas Ako made a presentation about the IP selection process on the 2021 IP-SOC event in Grenoble in December 2021.
High performance applications like server CPUs in a datacenter are typically made using the most advanced semiconductor processing technology. The latest process node provides benefits like lower power dissipation, higher transistor density and higher processing speed. However, IC designers developing chips in such advanced processes need to take extra efforts to ensure the chips areContinue reading “ESD protection for FinFET processes”
SOFICS - Solutions for ICs