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Selecting custom ESD IP for your next IC

Fabless semiconductor companies usually use third-party IP blocks when developing ICs. An important IP is on-chip ESD protection. Caution must be exercised in choosing the right ESD IP to avoid patent infringement and inefficient ESD clamps.

Thomas Ako made a presentation about the IP selection process on the 2021 IP-SOC event in Grenoble in December 2021.

Adapting Diode triggered SCRs (part 2)

In this article, I wish to introduce you to how we can use diode triggered silicon controlled rectifiers (DTSCRs) for on-chip ESD protection. I will explain how its 3 main parameters – trigger voltage, holding voltage and failure current – can be tuned in order to protect ICs with very different characteristics.

Diode triggered SCRs for ESD protection in CMOS ICs (part 1)

A specific case of an SCR-based solution which can be used to develop a wide range of on-chip ESD protection circuits is the diode triggered SCR (DTSCR). As its name implies, a DTSCR is constructed by combining an SCR with diodes to form a versatile circuit whose properties can be tuned at will to suit the requirements of the IC/interface which needs to be protected.

Latch-up in CMOS circuits: threat or opportunity (part 2)

Latch-up refers to unwanted short circuits which can occur in an integrated circuit whereby the power supply is inadvertently connected to the ground. In the first part (threat) of the article the focus was on the threat of latch-up and different ways to prevent it. In this part (opportunity) we discuss how (parasitic) SCR devices can be used in a positive way.

Latch-up in CMOS circuits: threat or opportunity (part 1)

In the first article about Latch-up, Thomas discusses the mechanism of the positive feedback loop between parasitic bipolar devices inside a CMOS inverter stage. He summarizes different causes and also provides ways to prevent latch-up threats.