on-chip ESD protection, custom/specialty Analog I/O’s and PHY’s
It’s Christmas 2021. The semiconductor industry is flooded with income: all fabs run at or above maximum capacity, volumes are in short supply while prices of wafers and ICs are floating up. Electronics are everywhere in our lock-down offices and private homes, and in many other systems and services that all of us use (almost) every day.
Sofics’ CEO outlook for 2022…
We often get the question: what is the CDM robustness of your ESD protection circuit? Though the question is clear, it is very hard to formulate a meaningful answer. CDM qualifies the performance of an IC or die in a specific package. Nevertheless, one expects an answer for the ESD circuit expressed in Volts.
This article discusses how VF-TLP analysis can be used to assess the CDM current capability of ESD devices.
How do you protect chip interfaces that require thin gate (core) transistors in advanced CMOS, SOI of FinFET processes? How do you ensure sufficient ESD robustness? Conventional ESD protection is not sufficient. Discover the background for that and a solution as well in this article. The answer is found in a strategy of local clamping with power-efficient devices.
This interview was held with Koen Verhaege, CEO of Sofics, June 2020Link to article: https://anysilicon.com/ceo-talk-koen-verhaege-sofics/ Tell me a bit about your background? How did you first get started with your company? I graduated from the University of Leuven, Belgium, with a degree in microelectronics in 1990 and started my professional career at IMEC in theContinue reading “ANYSILICON CEO TALK”
SOFICS - Solutions for ICs